The present invention relates to a device transforming each word of a .[.flow of series bits.]. .Iadd.serial bit stream .Iaddend.arriving at a first clock frequency into a word at a double frequency, the remaining time interval being occupied by filling bits. .[.Reversely,.]. .Iadd.In its opposite mode, .Iaddend.the device according to the invention selects, from a flow of bits arriving at a determined frequency, half these bits and transmits them at half bit rate.
FIG. 1 shows the function to be realized by a doubler in case of 8-bits words. Considering a word D.sub.F of a flow of successive words, wherein each bit d0 . . . d7 arrives at the frequency of a clock F, it is desired to obtain a word D.sub.2F comprising twice as many bits, here 16, wherein bits arrive at the rate of a clock 2F. Therefore, the word D.sub.2F contains the bits d0-d7 and filling bits r0-r7.
It is often useful to double the number of bits of a word for realizing operations with a greater accuracy. Once operations are completed, the 8 most significant bits are taken again in word D.sub.2F and they are transformed once more into a work D.sub.F in a dividing device.
An object of the invention is to provide a single device capable of operating either as a doubler or as a divider.